
CDCR83
DIRECT RAMBUS CLOCK GENERATOR
SCAS632B APRIL 2001 REVISED OCTOBER 2005
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
state transition latency specifications (continued)
PARAMETER
FROM
TO
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
t(powerdown)
Delay time, PWRDNB
↓ to the device in the
power-down mode
Normal
Powerdown
See Figure 8
1
ms
t(STOP)
Maximum time in CLKSTOP (STOPB = 0)
before reentering normal mode
(STOPB = 1)
STOPB
Normal
See Figure 10
100
s
t(ON)
Minimum time in normal mode (STOPB = 1)
before reentering CLKSTOP (STOPB = 0)
Normal
CLK stop
See Figure 10
100
ms
t(DISTLOCK)
Time from when CLK/CLKB output is
settled to when the phase error between
SYNCLKN and PCLKM falls within t(phase)
Unlocked
Locked
5
ms
All typical values are at VDD = 3.3 V, TA = 25°C.